An example of a disadvantaged memory circuit having an output device and external memory is shown in FIG. 1.
In FIG. 1 there are illustrated in block diagram form a static RAM 1 operating as an external memory, (hereinafter "SRAM"): an external memory controlling unit 2. (hereinafter an "SRAM controlling unit") for controlling SRAM 1 through a controlling line 2a and obtaining data stored in the SRAM through a data line 2b when the SRAM 1 is operated in an active state of operation, an output data controlling unit 3 for outputting data obtained by the SRAM controlling unit 2: and an output unit 4 controlled by an output signal from the output data controlling unit 3.
Next, an operation of the output device thus constructed will be described.
The SRAM controlling unit 2 operates to put the SRAM 1 into an active state through a control line 2a obtains data from the SRAM along a line 2b and transfers the data to the output data controlling unit 3 through a data line 6. The output data controlling unit 3 processes the data fed from the SRAM controlling unit 2 and then outputs the processed data to the output unit 4 along a line 7.
With the above-described disadvantaged memory circuit, a potential for a problem exists in that, in the case where the output unit 4 needs a large amount of current as shown in the upper plot of FIG. 2, a power source voltage may substantially drop as shown in the lower plot of FIG. 2 and become smaller than a minimum operation voltage of the SRAM during an output operation of the output unit 4. As a result of the voltage drop a reliable operation of SRAM cannot be guaranteed and thus there is a potential for an occurrence of an unreliable condition in data obtained from the SRAM 1 through the data line 2b. This in turn causes a delivery of unreliable data to the output unit 4.